Debugging Surface Mount Footprints With Time-Domain Reflectometry

As microwave designers push surface mount systems to higher frequencies of operation, the detailed layout of circuitry on a surface mount board becomes more important. This is particularly true for components that are designed to be low insertion loss and high return loss, such as Bias Tees, Couplers, Equalizers, Filters, Power Dividers, Limiters, and Switches.

These components are codesigned with a particular PCB footprint for optimal high frequency match, and this footprint is included in the datasheet. However, this footprint is based on a particular board stackup (circuit material and thickness), which a designer may not be using. A surface mount component has attachment pads that are typically more capacitive than a 50-ohm match would require, which means that some extra inductance is required to improve the match. In this article we will demonstrate a technique to experimentally determine the optimum inductive match for a surface mount component.

Time-domain reflectometry (TDR) is a useful tool traditionally used for applications such as determining cable length, fault locations, impedance changes, and various electro-mechanical features of transmission line cables that are either buried, very long, or dangerous to reach. At much higher frequencies, we can use this tool on much physically shorter transmission lines where we don’t have the same inaccessibility issues – instead the issue lies in the inability to see microscopic faults and invisible parasitics. Without a means to determine fault locations with the naked eye, TDR proves a powerful tool in visualizing impedance types and variations on a microstrip.