FEC Chips
The chips will be designed into modems for use in high-speed wireless Internet access applications including point-to-multipoint terrestrial and satellite connections. The chips are also designed for next-generation powerline modems enabling home or business networks through standard electrical outlets. In addition, these chips are ideal for wireless local loop (WLL) applications. Unlike cable or DSL Internet access solutions, wireless solutions are not hindered by central office distance limitations, squeezed by bandwidth tariffs or compromised by multiple users on the same cable.
The chips incorporate TPC technology, delivering up to 3 dB of additional coding gain over current solutions such as Reed Solomon/ Viterbi. This coding gain translates into a range of options that allow designers to increase capabilities or decrease system cost to best fit their application. With an Astro LE, designers can reduce required bandwidth, increase throughput or reduce transmitter power by 2x. Or designers can opt to increase range by 40 percent, reduce antenna size by 30 percent, or reduce the required noise figure of the receiver by 3 dB.
The products are single-chip Turbo Product Code (TPC) Forward Error Correction (FEC) encoder/decoders capable of up to 35 Mbit/sec coded data rates and code rates from 0.25 – 0.95. These devices integrate both a TPC encoder and decoder and can be operated in full- or half-duplex mode. Two versions are being introduced with support for block sizes of 2 and 4 Kbits. Both versions have 5V-tolerant inputs with a 3.3V I/O and 1.8V core operation. Rapid code change on-the-fly is included to balance speed and performance in any environment.
Advanced Hardware Architectures, Inc., 2365 NE Hopkins Court, Pullman, WA 99163. Tel: 509-334-1000; Fax: 509-334-9000.