Application Note: Using Sonnet EM Analysis With Cadence® Virtuoso® In RFIC Design

The Sonnet API for Cadence Virtuoso can import process stackup and drawing layer map information from a variety of sources, including Assura process files, Helic technology files, Agilent technology (*.tch,) files as well as existing Sonnet Material (*.matl) and pre-existing Sonnet project files. Complete process stackup and layout-to-material associations can be imported with a single import for any given structure within a process technology. Often these process files come with the technology PDK supported by the parent EDA framework. Alternatively, a stackup definition may be created manually and stored in the Sonnet API by the EDA tool flow manager for use in all structures simulated for a given process technology.

The Sonnet API for Virtuoso also includes the ability to display an internal simulation progress bar, implementation of Sonnet's patented Co-calibrated Port technology for internal port group calibration and de-embedding, single-click access to show circuit descritization, "simulate and release" capability to allow EM simulation to continue without locking out the Virtuoso framework, and the ability to automatically create a symbol for the Cadence Schematic Composer in the form of a layout look alike instance. Sonnet provides both frequency domain model extraction in the form of S, Y or Z-parameters, as well as the ability to provide a Spice model extraction using the Sonnet Broadband Model extractor.